MC68HC08AZ32A Datasheet, PDF (231/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Registers
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission.
The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and
the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. See
16.5.7 Mode Fault Error. A 1 on the SS pin does not affect the state of the SPI state machine in any
way.
SPWOM — SPI Wired-OR Mode
This read/write bit disables the pull-up devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See 16.8
Resetting the SPI. Reset clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
16.12.2 SPI Status and Control Register (SPSCR)
The SPI status and control register contains flags to signal the following conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform the following functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address: $0011
Bit 7
Read: SPRF
Write:
Reset: 0
6
ERRIE
5
OVRF
0
0
= Unimplemented
4
MODF
0
3
SPTE
1
2
MODFEN
0
1
SPR1
0
Figure 16-14. SPI Status and Control Register (SPSCR)
Bit 0
SPR0
0
SPRF — SPI Receiver Full
This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
231