MC68HC08AZ32A Datasheet, PDF (227/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Power Modes
16.9 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.9.1 WAIT Mode
The SPI module remains active after the execution of a WAIT instruction. In WAIT mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of WAIT mode.
If SPI module functions are not required during WAIT mode, power consumption can be reduced by
disabling the SPI module before executing the WAIT instruction.
To exit WAIT mode when an overflow condition occurs, the OVRF bit should be enabled to generate CPU
interrupt requests by setting the error interrupt enable bit (ERRIE). See 16.6 Interrupts.
16.9.2 STOP Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after an external interrupt. If STOP mode is exited by
reset, any transfer in progress is aborted, and the SPI is reset.
16.10 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 15.7.3 SIM Break Flag Control Register (SBFCR).
To allow software to clear status bits during a break interrupt, a 1 should be written to the BCFE bit. If a
status bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, a 0 should be written to the BCFE bit. With BCFE at 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a two-step read/write clearing procedure. If software does the first step on such a
bit before the break, the bit cannot change during the break state as long as BCFE is a 0. After the break,
the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the data register
in break mode will not initiate a transmission, nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
16.11 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port.
• MISO — data received
• MOSI — data transmitted
• SPSCK — serial clock
• SS — slave select
• V_SS — clock ground
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
227