MC68HC08AZ32A Datasheet, PDF (123/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Protocol Violation Protection
11.7 Protocol Violation Protection
The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming
errors. The protection logic implements the following features:
• The receive and transmit error counters cannot be written or otherwise manipulated.
• All registers which control the configuration of the MSCAN08 can not be modified while the
MSCAN08 is on-line. The SFTRES bit in the MSCAN08 module control register (see 11.13.1
MSCAN08 Module Control Register 0) serves as a lock to protect the following registers:
– MSCAN08 module control register 1 (CMCR1)
– MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1)
– MSCAN08 identifier acceptance control register (CIDAC)
– MSCAN08 identifier acceptance registers (CIDAR0–CIDAR3)
– MSCAN08 identifier mask registers (CIDMR0–CIDMR3)
• The TxCAN pin is forced to recessive when the MSCAN08 is in any of the low-power modes.
11.8 Low Power Modes
In addition to normal mode, the MSCAN08 has three modes with reduced power consumption:
• Sleep mode
• Soft reset mode
• Power down modes
In sleep and soft reset mode, power consumption is reduced by stopping all clocks except those to access
the registers. In power down mode, all clocks are stopped and no power is consumed.
The WAIT and STOP instructions put the MCU in low-power consumption standby modes. Table 11-2
summarizes the combinations of MSCAN08 and CPU modes. A particular combination of modes is
entered for the given settings of the bits SLPAK and SFTRES. For all modes, an MSCAN wakeup interrupt
can occur only if SLPAK = WUPIE = 1.
.
Table 11-2. MSCAN08 versus CPU Operating Modes
MSCAN Mode
Power Down
Sleep
Soft Reset
Normal
1. ‘X’ means don’t care.
CPU Mode
STOP
SLPAK = X⁽¹⁾
SFTRES = X
WAIT or RUN
SLPAK = 1
SFTRES = 0
SLPAK = 0
SFTRES = 1
SLPAK = 0
SFTRES = 0
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
123