MC68HC08AZ32A Datasheet, PDF (279/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Monitor Module (MON)
1 µF
1 µF
DB9
2
3
5
V_DD
MC68HC08AZ32A
1 _C1+
+
3 _C1–
4 _C2+
+
5 _C2–
7
8
MAX232
V_CC ¹⁶
GND ¹⁵
V+ ²
V– ⁶
10
9
10 k
47 pF
V_DD
+
1 µF
1 µF
+
27 pF
10 MΩ
4.9152 MHz
1 kΩ
1 µF
+
74HC125
6
5
74HC125
2
3
4
V_DD
9.1 V
10 kΩ
RST
OSC2
OSC1
IRQ
PTA0
V_DD
V_DDA
PTC3
PTC0
PTC1
V_SSA
V_SS
1
V_DD
0.1 µF
V_DD
10 k
10 k
10 k
Figure 19-8. Normal Monitor Mode Circuit
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
19.3.1.1 Monitor Mode Entry
Table 19-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication provided the pin and clock
conditions are met.
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTC0, PTC1, and PTC3 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
Table 19-1. Mode Selection
IRQ
PTC0 PTC1 PTA0 PTC3 Mode
CGMOUT
Bus Frequency
C-----G----M-----X-----C----L---K---
2
V_TSTI⁽¹⁾
1
0
1
1
Monitor
or
C-----G----M-----V-----C----L---K---
2
V_TSTI⁽¹⁾
1
0
1
0
Monitor
CGMXCLK
1. For V_TST, 20.5 5.0 Volt DC Electrical Characteristics and 20.2 Maximum Ratings.
C-----G----M------O----U----T---
2
C-----G----M------O----U----T---
2
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
279