MC68HC08AZ32A Datasheet, PDF (309/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Revision History
Major Changes Between Revision 2.0 and Revision 1.0
The following table lists the major changes between the current revision of the MC68HC08AZ32A
Technical Data Book and revision 1.0.
Section Affected
Throughout
Description of Change
Reformatted document to current publications standards
Major Changes Between Revision 1.0 and Revision 0.0
The following table lists the major changes between the revision 1.0 of the MC68HC08AZ32A Technical
Data Book and the initial release at revision 0.0.
Section Affected
Description of Change
General Description
Corrected text in numerous pin desriptions.
Corrected Table 1-1 - External Pins Summary with which pins have hysteresis.
Added missing modules to Table 1-3 - Clock Source Summary
Memory Map
Corrected type errors.
Corrected various addresses and register names in Figure 2-1 - Memory Map.
Corrected numerous register bit descriptions in Figure 2-2 - I/O Data, Status and
Control Registers to match module sections.
Added Additional Status and Control Registers section and moved register
descriptions accordingly. Corrected bit descriptions to match module sections.
EEPROM
Section altered significantly to better align module descriptions across groups within
Freescale using 0.5µ TSMC/SST FLASH. Numerous additions submitted by
applications engineering for further clarification of functional operation.
Clock Generator Module
(CGM)
Corrected clock signal names and associated timing parameters for consistency and to
match signal naming conventions.
Additional textual description added to Reaction Time Calculation subsection.
Mask Options
Corrected descriptions of LVIRST and LVIPWR bits
Break Module
Corrected description of BRKSCR register
System Integration Module (SIM) Corrected various type errors in SBSR and SBFCR register bit descriptions
Monitor ROM (MON)
Modified Figure 11-1 - Monitor Mode Circuit based upon recommendations from
applications engineering.
Corrected type errors.
Corrected Figure 11-6 - Monitor Mode Entry Timing.
Computer Operating Properly
(COP)
Corrected references to COPL (now COPRS).
Corrected type errors.
Low Voltage Inhibit (LVI)
Corrected functional description and revised Figure 13-1 - LVI Module Block Diagram
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
309