MC68HC08AZ32A Datasheet, PDF (110/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Mask Options
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See Chapter 9 Low-Voltage Inhibit (LVI)
Module).
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. See Chapter 9 Low-Voltage Inhibit (LVI) Module).
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096
CGMXCLK cycle delay.
1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles
If using an external crystal oscillator, the SSREC bit should not be set.
COPRS — COP Rate Select
COPRS is similar to COPL (please note that the logic is reversed) as it determines the timeout period
for the COP.
1 = COP timeout period is 8176 CGMXCLK cycles.
0 = COP timeout period is 262,128 CGMXCLK cycles.
STOP — STOP Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 5 Computer Operating Properly (COP) Module.
1 = COP module disabled
0 = COP module enabled
NOTE
Extra care should be exercised when selecting mask option registers since
other M68HC08 Family parts may have different options. It is the user’s
responsibility to correctly define the mask option registers. If in doubt, check
with your local field applications representative.
Address: $FE09
Bit 7
6
5
4
3
2
Read: EEDIVCLK 0
EESEC EEMONSEC AZ32A
0
1
Bit 0
0
0
Write:
Reset:
= Unimplemented
Unaffected by reset
Figure 10-2. Mask Option Register B (MORB)
MC68HC08AZ32A Data Sheet, Rev. 2
110
Freescale Semiconductor