MC68HC08AZ32A Datasheet, PDF (215/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Pin Name Conventions and I/O Register Addresses
16.3 Pin Name Conventions and I/O Register Addresses
The generic names of the SPI input/output (I/O) pins are:
• SS (slave select)
• SPSCK (SPI serial clock)
• MOSI (master out slave in)
• MISO (master in slave out)
The SPI shares four I/O pins with a parallel I/O port. The full name of an SPI pin reflects the name of the
shared port pin. Table 16-1 shows the full names of the SPI I/O pins. The generic pin names appear in
the text that follows.
Table 16-1. Pin Name Conventions
SPI Generic Pin Names:
MISO
MOSI
SS
SCK
Full SPI Pin Names: PTE5/MISO PTE6/MOSI PTE4/SS PTE7/SPSCK
16.4 Functional Description
Figure 16-2 summarizes the SPI I/O registers and Figure 16-3 shows the structure of the SPI module.
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be
interrupt-driven. All SPI interrupts can be serviced by the CPU.
The following paragraphs describe the operation of the SPI module.
Addr.
$0010
$0011
$0012
Name
Bit 7
6
5
4
3
2
SPI Control Register
(SPCR)
See page 230.
Read:
SPRIE
Write:
Reset: 0
R SPMSTR CPOL CPHA SPWOM
0
1
0
1
0
SPI Status and Control Register
(SPSCR)
See page 231.
Read:
Write:
Reset:
SPRF
0
ERRIE
0
OVRF
0
MODF
0
SPTE
MODFEN
1
0
SPI Data Register ^{Read: R7}
R6
R5
R4
R3
R2
(SPDR) Write: T7
T6
T5
T4
T3
T2
See page 233. _Reset:
Unaffected by reset
R = Reserved
= Unimplemented
Figure 16-2. SPI I/O Register Summary
1
SPE
0
SPR1
0
R1
T1
Bit 0
SPTIE
0
SPR0
0
R0
T0
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
215