MC68HC08AZ32A Datasheet, PDF (37/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Additional Status and Control Registers
2.3 Additional Status and Control Registers
Selected addresses in the range $FE00 to $FFCB contain additional status and control registers as
shown in Figure 2-3. A noted exception is the COP control register (COPCTL) at address $FFFF.
Addr.
Name
Bit 7
6
5
4
3
2
1
Read:
BW
SIM Break Status Register
R
R
R
R
R
R
$FE00
(SBSR) Write:
0
See page 210. _Reset:
0
SIM Reset Status Register ^{Read: POR}
PIN
COP
ILOP
ILAD
0
LVI
$FE01
(SRSR) Write:
See page 210. _POR:
1
0
0
0
0
0
0
SIM Break Flag Control ^Read: _BCFE
R
R
R
R
R
R
$FE03
Register (SBFCR) Write:
See page 211.
Reset: 0
Read: EEDIVCLK 0
EESEC EEMONSEC AZ32A
0
0
Mask Option Register B
$FE09
(MORB) Write:
See page 110. _Reset:
Unaffected by reset
Break Address Register ^Read: _{Bit 15}
14
13
12
11
10
9
$FE0C
High (BRKH) Write:
See page 277. _Reset:
0
0
0
0
0
0
0
Break Address Register ^Read: _{Bit 7}
6
5
4
3
2
1
$FE0D
Low (BRKL) Write:
See page 277.
Reset: 0
0
0
0
0
0
0
Read:
0
0
0
0
0
Break Status and Control
BRKE BRKA
$FE0E
Register (BRKSCR) Write:
See page 276. _Reset:
0
0
0
0
0
0
0
LVI Status Register ^{Read: LVIOUT}
0
0
0
0
0
0
$FE0F
(LVISR) Write:
See page 107. _Reset:
0
0
0
0
0
0
0
$FE10
EEDIV High Nonvolatile ^{Read: EEDIVS-}
Register (EEDIVHNVR) Write: ^ECD
R
See page 50.
Reset:
R
R
R
EEDIV10 EEDIV9
Unaffected by reset; $FF when blank
$FE11
Read:
EEDIV Low Nonvolatile
Register (EEDIVLNVR) Write:
See page 50. _Reset:
EEDIV7
EEDIV6
EEDIV5 EEDIV4 EEDIV3 EE2DIV
Unaffected by reset; $FF when blank
EEDIV1
= Unimplemented
R
= Reserved
Figure 2-3. Additional Status and Control Registers (Sheet 1 of 2)
Bit 0
R
0
0
R
0
Bit 8
0
Bit 0
0
0
0
0
0
EEDIV8
EEDIV0
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
37