MC68HC08AZ32A Datasheet, PDF (275/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

IAB[15:8]
Break Module (BRK)
IAB[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BKPT
(TO SIM)
IAB[7:0]
Figure 19-2. Break Module Block Diagram
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
Break Address Register High ^Read: _{Bit 15}
14
13
12
11
10
$FE0C
(BRKH) Write:
See page 277. _Reset:
0
0
0
0
0
0
9
Bit 8
0
0
Break Address Register Low ^Read: _{Bit 7}
6
5
4
3
2
1
Bit 0
$FE0D
(BRKL) Write:
See page 277. _Reset:
0
0
0
0
0
0
0
0
Break Status and Control ^Read: _BRKE
BRKA
0
0
0
0
0
0
$FE0E
Register (BRKSCR) Write:
R
R
R
R
R
R
See page 276. _Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 19-3. Break I/O Register Summary
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
275