MC68HC08AZ32A Datasheet, PDF (77/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Chapter 5
Computer Operating Properly (COP) Module
5.1 Introduction
This section describes the computer operating properly (COP) module, a free-running counter that
generates a reset if allowed to overflow. The COP module helps software recover from runaway code.
Prevent a COP reset by periodically clearing the COP counter.
5.2 Functional Description
Figure 5-1 shows the structure of the COP module.
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. COP timeouts are determined strictly by the CGM crystal oscillator clock signal (CGMXCLK), not
the CGMOUT signal (see Figure 4-1. CGM Block Diagram).
If not cleared by software, the COP counter overflows and generates an asynchronous reset after 8176
or 262,128 CGMXCLK cycles, depending upon COPS bit in the MORA register ($001F). (See Chapter 10
Mask Options.) With a 4.9152-MHz crystal and the COPS bit in the MORA register ($001F) set to a 1, the
COP timeout period is approximately 53.3 ms. Writing any value to location $FFFF before overflow occurs
clears the COP counter, clears stages 12 through 5 of the SIM counter, and prevents reset. A CPU
interrupt routine can be used to clear the COP.
NOTE
The COP should be serviced as soon as possible out of reset and before
entering or after exiting stop mode to guarantee the maximum selected
amount of time before the first timeout.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the SIM reset status
register (SRSR). See 15.7.2 SIM Reset Status Register (SRSR).
While the microcontroller is in monitor mode, the COP module is disabled if the RST pin or the IRQ pin is
held at V_TST (see 20.5 5.0 Volt DC Electrical Characteristics). During a break state, V_TST on the RST pin
disables the COP module.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
The one exception to this is wait mode (see 5.7.1 Wait Mode).
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
77