MC68HC08AZ32A Datasheet, PDF (152/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Programmable Interrupt Timer (PIT)
12.7.2 PIT Counter Registers
The two read-only PIT counter registers contain the high and low bytes of the value in the PIT counter.
Reading the high byte (PCNTH) latches the contents of the low byte (PCNTL) into a buffer. Subsequent
reads of PCNTH do not affect the latched PCNTL value until PCNTL is read. Reset clears the PIT counter
registers. Setting the PIT reset bit (PRST) also clears the PIT counter registers.
NOTE
If you read PCNTH during a break interrupt, be sure to unlatch PCNTL by
reading PCNTL before exiting the break interrupt. Otherwise, PCNTL
retains the value latched during the break.
Address: $004C
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
Address: $004D
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-5. PIT Counter Registers (PCNTH–PCNTL)
12.7.3 PIT Counter Modulo Registers
The read/write PIT modulo registers contain the modulo value for the PIT counter. When the PIT counter
reaches the modulo value the overflow flag (POF) becomes set and the PIT counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (PMODH) inhibits the POF bit and overflow
interrupts until the low byte (PMODL) is written. Reset sets the PIT counter modulo registers.
Address: $004E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
Reset: 1
1
1
1
1
1
9
Bit 8
1
1
Address: $004F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 12-6. PIT Counter Modulo Registers (PMODH–PMODL)
NOTE
Reset the PIT counter before writing to the PIT counter modulo registers.
MC68HC08AZ32A Data Sheet, Rev. 2
152
Freescale Semiconductor