MC68HC08AZ32A Datasheet, PDF (149/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

PIT Counter Prescaler
Addr.
Register Name
Bit 7
6
5
4
3
PIT Status and Control ^{Read: POF}
POIE PSTOP
0
0
$004B
Register (PSC) Write: 0
PRST
See page 150. _Reset:
0
0
1
0
0
PIT Counter Register High ^{Read: Bit 15}
14
13
12
11
$004C
(PCNTH) Write:
See page 152. _Reset:
0
0
0
0
0
PIT Counter Register Low ^{Read: Bit 7}
6
5
4
3
$004D
(PCNTL) Write:
See page 152. _Reset:
0
0
0
0
0
PIT Counter Modulo ^Read: _{Bit 15}
14
13
12
11
$004E Register High (PMODH) Write:
See page 152. _Reset:
1
1
1
1
1
PIT Counter Modulo ^Read: _{Bit 7}
6
5
4
3
$004F Register Low (PMODL) Write:
See page 152. _Reset:
1
1
1
1
1
=Unimplemented
Figure 12-3. PIT I/O Register Summary
2
PPS2
0
10
0
2
0
10
1
2
1
1
PPS1
0
9
0
1
0
9
1
1
1
Bit 0
PPS0
0
Bit 8
0
Bit 0
0
Bit 8
1
Bit 0
1
12.4 PIT Counter Prescaler
The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PPS[2:0], in the status and control register select
the PIT clock source.
The value in the PIT counter modulo registers and the selected prescaler output determines the frequency
of the periodic interrupt. The PIT overflow flag (POF) is set when the PIT counter value reaches the
modulo value programmed in the PIT counter modulo registers. The PIT interrupt enable bit, POIE,
enables PIT overflow CPU interrupt requests. POF and POIE are in the PIT status and control register.
12.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
12.5.1 Wait Mode
The PIT remains active after the execution of a WAIT instruction. In wait mode the PIT registers are not
accessible by the CPU. Any enabled CPU interrupt request from the PIT can bring the MCU out of wait
mode.
If PIT functions are not required during wait mode, reduce power consumption by stopping the PIT before
executing the WAIT instruction.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
149