MC68HC08AZ32A Datasheet, PDF (166/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Input/Output (I/O) Ports
PTF[6:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0].
TACH[5:2] — Timer A Channel I/O Bits
The PTF3/TACH5–PTF0/TACH2 pins are the TIM input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF3/TACH5–PTF0/TACH2 pins are timer channel
I/O pins or general-purpose I/O pins.
TBCH[1:0] — Timer B Channel I/O Bits
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0 pins are timer channel
I/O pins or general-purpose I/O pins. See 18.8.1 TIMB Status and Control Register.
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by TIMA and TIMB. However, the DDRF bits
always determine whether reading port F returns the states of the latches
or the states of the pins. See Table 13-6.
13.7.2 Data Direction Register F (DDRF)
Data direction register F determines whether each port F pin is an input or an output. Writing a 1 to a
DDRF bit enables the output buffer for the corresponding port F pin; a 0 disables the output buffer.
Address: $000D
Bit 7
Read: 0
Write:
Reset: 0
6
5
DDRF6 DDRF5
0
0
= Unimplemented
4
DDRF4
0
3
DDRF3
0
2
DDRF2
0
1
DDRF1
0
Bit 0
DDRF0
0
Figure 13-18. Data Direction Register F (DDRF)
DDRF[6:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins
as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
MC68HC08AZ32A Data Sheet, Rev. 2
166
Freescale Semiconductor