MC68HC08AZ32A Datasheet, PDF (33/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Section
Addr.
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
Name
Bit 7
6
5
4
3
2
1
SCI Baud Rate Register ^Read:
(SCBR) Write:
See page 194. _Reset:
0
SCP1
SCP0
R
SCR2 SCR1
0
0
0
0
0
0
IRQ Status and Control ^Read:
0
0
0
Register (ISCR) Write:
See page 97. _Reset:
0
0
0
0
IRQF
0
IMASK
ACK
0
0
0
0
Keyboard Status/Control ^Read:
0
0
0
(KBSCR) Write:
See page 103. _Reset:
0
0
0
0
KEYF
0
IMASKK
ACKK
0
0
0
0
PLL Control Register ^Read: _PLLIE
PLLF
PLLON
BCS
1
(PCTL) Write:
See page 69. _Reset:
0
0
1
0
1
1
1
1
1
PLL Bandwidth Control ^Read: _AUTO
LOCK
ACQ
XLD
0
0
0
Register (PBWC) Write:
See page 70. _Reset:
0
0
0
0
0
0
0
PLL Programming Register ^Read:
(PPG) Write:
See page 71. _Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
Mask Option Register A ^Read:
(MORA) Write:
See page 109. _Reset:
LVISTOP
ROMSEC
LVIRST
LVIPWR SSREC COPRS
Unaffected by reset
STOP
Timer A Status and Control ^{Read: TOF}
TOIE TSTOP
0
0
PS2
PS1
Register (TASC) Write: 0
TRST
R
See page 247. _Reset:
0
0
1
0
0
0
0
Keyboard Interrupt Enable ^Read:
0
0
Register (KBIER) Write:
See page 104. _Reset:
0
0
0
KBIE4
KBIE3
KBIE2 KBIE1
0
0
0
0
0
Timer A Counter Register ^{Read: Bit 15}
14
13
High (TACNTH) Write:
See page 248. _Reset:
0
0
0
12
11
10
9
0
0
0
0
Timer A Counter Register ^{Read: Bit 7}
6
5
4
3
2
1
Low (TACNTL) Write:
See page 248. _Reset:
0
0
0
0
0
0
0
Timer A Modulo Register ^Read: _{Bit 15}
14
13
High (TAMODH) Write:
See page 249. _Reset:
1
1
1
12
11
10
9
1
1
1
1
Timer A Modulo Register ^Read: _{Bit 7}
6
5
4
3
2
1
Low (TAMODL) Write:
See page 249. _Reset:
1
1
1
1
1
1
1
= Unimplemented
R
= Reserved
Figure 2-2. I/O Data, Status and Control Registers (Sheet 3 of 6)
Bit 0
SCR0
0
MODE
0
MODEK
0
1
1
0
0
VRS4
0
COPD
PS0
0
KBIE0
0
Bit 8
0
Bit 0
0
Bit 8
1
Bit 0
1
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
33