MC68HC08AZ32A Datasheet, PDF (273/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Chapter 19
Development Support
19.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode
entry methods.
19.2 Break Module (BRK)
The break module can generate a break interrupt which stops normal program flow at a defined address
in order to begin execution of a background program.
Features include:
• Accessible I/O registers during the break interrupt
• CPU-generated break Interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
19.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction
register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The
program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a 1 to the BRKA bit in the break status and control register (BRKSCR).
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal operation. Figure 19-2 shows the structure
of the break module.
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
273