MC68HC08AZ32A Datasheet, PDF (144/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

MSCAN08 Controller (MSCAN08)
11.13.10 MSCAN08 Receive Error Counter
Address: $050E
Bit 7
Read: RXERR7
Write:
6
RXERR6
5
RXERR5
4
RXERR4
3
RXERR3
2
RXERR2
1
RXERR1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 11-25. Receiver Error Counter (CRXERR)
Bit 0
RXERR0
0
This read-only register reflects the status of the MSCAN08 receive error counter.
11.13.11 MSCAN08 Transmit Error Counter
Address: $050F
Read:
Write:
Bit 7
TXERR7
6
TXERR6
5
TXERR5
4
TXERR4
3
TXERR3
2
TXERR2
1
TXERR1
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 11-26. Transmit Error Counter (CTXERR)
Bit 0
TXERR0
0
This read-only register reflects the status of the MSCAN08 transmit error counter.
NOTE
Both error counters may only be read when in sleep or soft reset mode.
11.13.12 MSCAN08 Identifier Acceptance Registers
On reception each message is written into the background receive buffer. The CPU is only signalled to
read the message, however, if it passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the next message (dropped).
The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming
messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only
the first two (CIDMR0/CIDMR1 and CIDAR0/CIDAR1) are applied.
MC68HC08AZ32A Data Sheet, Rev. 2
144
Freescale Semiconductor