MC68HC08AZ32A Datasheet, PDF (223/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

BYTE 1
SPI RECEIVE
1
COMPLETE
SPRF
BYTE 2
5
BYTE 3
7
BYTE 4
11
Transmission Formats
OVRF
READ SPSCR
2
4
6
9
12
14
READ SPDR
3
8
10
13
1 BYTE 1 SETS SPRF BIT.
2 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
3 CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
5 BYTE 2 SETS SPRF BIT.
6 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
7 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
8 CPU READS BYTE 2 IN SPDR, CLEARING SPFR BIT.
9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
12 CPU READS SPSCR.
13 CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
14 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 16-9. Clearing SPRF When OVRF Interrupt is Not Enabled
16.5.7 Mode Fault Error
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the
MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is
cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and OVRF can
generate a receiver/error CPU interrupt request. See Figure 16-10. It is not possible to enable only MODF
or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents
MODF from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS
goes low. A mode fault in a master SPI causes the following events to occur:
• If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request.
• The SPE bit is cleared.
• The SPTE bit is set.
• The SPI state counter is cleared.
• The data direction register of the shared I/O port regains control of port drivers.
NOTE
To prevent bus contention with another master SPI after a mode fault error,
clear all data direction register (DDR) bits associated with the SPI shared
port pins.
Setting the MODF flag (SPSCR) does not clear the SPMSTR bit. Reading
SPMSTR when MODF = 1 will indicate a MODE fault error occurred in
either master mode or slave mode.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
223