MC68HC08AZ32A Datasheet, PDF (201/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Reset and System Initialization
15.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter, 15.3.3 SIM Counter, but an external reset does not. Each of the
resets sets a corresponding bit in the SIM reset status register (SRSR). (See 15.7 SIM Registers.)
15.3.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register
(SRSR) is set as long as RST is held low for at least the minimum t_RL time. Figure 15-5 shows the relative
timing.
CGMOUT
RST
IAB
PC
VECT H VECT L
Figure 15-5. External Reset Timing
15.3.2 Active Resets From Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow for resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles.
See Figure 15-6. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
or POR. See Figure 15-7. Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK
cycles, during which the SIM forces the RST pin low. The internal reset signal then follows the sequence
from the falling edge of RST as shown in Figure 15-6.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
201