MC68HC08AZ32A Datasheet, PDF (266/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module B (TIMB)
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/ATD12/TBCLK pin or one of the seven prescaler outputs
as the input to the TIMB counter as Table 18-1 shows. Reset clears the PS[2:0] bits.
Table 18-1. Prescaler Selection
PS[2:0]
000
001
010
011
100
101
110
111
TIMB Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
PTD4/ATD12/TBCLK
18.8.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter.
Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB
counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
NOTE
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by
reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL
retains the value latched during the break.
Register Name and Address
TBCNTH — $0041
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
Write: R
R
R
R
R
R
Reset: 0
0
0
0
0
0
Register Name and Address
TBCNTL — $0042
Bit 7
6
5
4
3
2
Read: Bit 7
6
5
4
3
2
Write: R
R
R
R
R
R
Reset: 0
0
0
0
0
0
R = Reserved
1
Bit 0
9
Bit 8
R
R
0
0
1
Bit 0
1
Bit 0
R
R
0
0
Figure 18-6. TIMB Counter Registers (TBCNTH and TBCNTL)
MC68HC08AZ32A Data Sheet, Rev. 2
266
Freescale Semiconductor