MC68HC08AZ32A Datasheet, PDF (199/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

STOP/WAIT
CONTROL
SIM
COUNTER
÷2
CLOCK
CONTROL
CLOCK GENERATORS
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 15-2. SIM Block Diagram
Addr.
$FE00
$FE01
$FE03
Name
Bit 7
6
5
4
3
2
SIM Break Status Register ^Read:
R
R
R
R
R
R
(SBSR) Write:
See page 210. _Reset:
SIM Reset Status Register ^{Read: POR}
PIN
COP
ILOP
ILAD
0
(SRSR) Write:
See page 210. _POR:
1
0
0
0
0
0
SIM Break Flag Control ^Read: _BCFE
R
R
Register (SBFCR) Write:
See page 211. _{Reset: 0}
R = Reserved
R
R
R
= Unimplemented
Figure 15-3. SIM I/O Register Summary
1
Bit 0
BW
R
0
0
LVI
0
0
0
R
R
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
199