MC68HC08AZ32A Datasheet, PDF (224/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Peripheral Interface (SPI)
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission.
When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes
back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins
when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK
returns to its IDLE level following the shift of the last data bit. See 16.5 Transmission Formats.
NOTE
When CPHA = 0, a MODF occurs if a slave is selected (SS is low) and later
deselected (SS is high) even if no SPSCK is sent to that slave. This
happens because SS at 0 indicates the start of the transmission (MISO
driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave
can be selected and then later deselected with no transmission occurring.
Therefore, MODF does not occur since a transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the
ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort
the SPI transmission by toggling the SPE bit of the slave.
NOTE
A high on the SS pin of a slave SPI puts the MISO pin in a high-impedance
state. Also, the slave SPI ignores all incoming SPSCK clocks, even if a
transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR register. This entire clearing
procedure must occur with no MODF condition existing or else the flag will not be cleared.
16.6 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 16-2 and
Figure 16-10.
Table 16-2. SPI Interrupts
Flag
SPTE (transmitter empty)
SPRF (receiver full)
OVRF (overflow)
MODF (mode fault)
Request
SPI transmitter CPU interrupt request (SPTIE = 1)
SPI receiver CPU interrupt request (SPRIE = 1)
SPI receiver/error interrupt request (SPRIE = 1, ERRIE = 1)
SPI receiver/error interrupt request (SPRIE = 1, ERRIE = 1, MODFEN = 1)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt
requests, provided that the SPI is enabled (SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a
receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
flag is enabled to generate receiver/error CPU interrupt requests.
MC68HC08AZ32A Data Sheet, Rev. 2
224
Freescale Semiconductor