MC68HC08AZ32A Datasheet, PDF (220/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Peripheral Interface (SPI)
SCK CYCLE #
(FOR REFERENCE)
1
2
3
4
5
6
7
SCK (CPOL =0)
SCK (CPOL =1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SS (TO SLAVE)
CAPTURE STROBE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Figure 16-6. Transmission Format (CPHA = 1)
8
LSB
LSB
16.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions are started by a software write to
the SPDR. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial
state of the SCK signal. When CPHA = 0, the SCK signal remains inactive for the first half of the first SCK
cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. See Figure 16-7. The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits are set to
conserve power. SCK edges occur halfway through the low time of the internal MCU clock. Since the SPI
clock is free-running, it is uncertain where the write to the SPDR will occur relative to the slower SCK. This
uncertainty causes the variation in the initiation delay shown in Figure 16-7. This delay will be no longer
than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus
cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
16.5.5 Error Conditions
The following flags signal SPI error conditions:
• Overflow (OVRF) — failing to read the SPI data register before the next byte enters the shift
register results in the OVRF bit becoming set. The new byte does not transfer to the receive data
register, and the unread byte still can be read by accessing the SPI data register. OVRF is in the
SPI status and control register.
• Mode fault error (MODF) — the MODF bit indicates that the voltage on the slave select pin (SS) is
inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
MC68HC08AZ32A Data Sheet, Rev. 2
220
Freescale Semiconductor