MC68HC08AZ32A Datasheet, PDF (106/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI) Module)
V_DD
LOW V_DD
DETECTOR
LVIPWR
FROM MORA
CPU CLOCK
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
V_DD
DIGITAL FILTER
FROM MORA
LVIRST
ANLGTRIP
Stop Mode
Filter Bypass
LVIOUT
LVISTOP
FROM MORA
Figure 9-1. LVI Module Block Diagram
LVI RESET
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$FE0F
LVI Status Register ^{Read: LVIOUT}
0
0
0
0
0
0
0
(LVISR) Write:
See page 107. _Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-2. I/O Register Summary
9.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the LVI_TRIPF level, software can monitor V_DD by
polling the LVIOUT bit. In the mask option register, the LVIPWR bit must be at a 1 to enable the LVI
module and the LVIRST bit must be a 0 to disable LVI resets.
9.3.2 Forced Reset Operation
In applications that require V_DD to remain above the LVI_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls to the LVI_TRIPF level and remains at or below that level for nine
or more consecutive CPU cycles. In the mask option register, the LVIPWR and LVIRST bits must be 1s
to enable the LVI module and to enable LVI resets.
9.3.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI
module to reset the MCU,V_DD must remain at or below the LVI_TRIPF level for nine or more consecutive
CPU cycles. V_DD must be above LVI_TRIPR for only one CPU cycle to bring the MCU out of reset.
MC68HC08AZ32A Data Sheet, Rev. 2
106
Freescale Semiconductor