MC68HC08AZ32A Datasheet, PDF (249/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Registers
Register Name and Address
TAMODH — $0024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
Write:
Reset: 1
1
1
1
1
1
1
1
Register Name and Address
TAMODL — $0025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 17-7. TIMA Counter Modulo Registers (TAMODH and TAMODL)
NOTE
Reset the TIMA counter before writing to the TIMA counter modulo registers.
17.8.4 TIMA Channel Status and Control Registers
Each of the TIMA channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare or PWM operation
• Selects high, low or toggling output on output compare
• Selects rising edge, falling edge or any edge as the active input capture trigger
• Selects output toggling on TIMA overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Address
TASC0 — $0026
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
CH0F
0
0
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
CH0MAX
0
Register Name and Address
TASC1 — $0029
Bit 7
6
5
4
Read: CH1F
0
CH1IE
MS1A
Write: 0
R
Reset: 0
0
0
0
R
= Reserved
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Figure 17-8. TIMA Channel Status and Control Registers
(TASC0–TASC5) (Sheet 1 of 2)
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
249