MC68HC08AZ32A Datasheet, PDF (62/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
OSC1
CGMRDV
CGMRCLK
V_DDA CGMXFC
CLOCK
SELECT
÷2
CIRCUIT
BCS
V_SS
VRS7–VRS4
PHASE
DETECTOR
LOCK
DETECTOR
LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
PLL ANALOG
BANDWIDTH
CONTROL
INTERRUPT
CONTROL
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
PTC3
MONITOR MODE
USER MODE
CGMINT
LOCK
AUTO ACQ
MUL7–MUL4
PLLIE PLLF
CGMVDV
FREQUENCY
DIVIDER
CGMVCLK
Figure 4-1. CGM Block Diagram
Addr.
$001C
$001D
$001E
Register Name
PLL Control Register ^Read:
(PCTL) Write:
See page 69. _Reset:
PLL Bandwidth Control ^Read:
Register (PBWC) Write:
See page 70. _Reset:
PLL Programming Register ^Read:
(PPG) Write:
See page 71. _Reset:
Bit 7
PLLIE
0
AUTO
0
MUL7
0
6
5
PLLF
PLLON
0
1
LOCK
ACQ
0
0
MUL6
MUL5
1
1
= Unimplemented
4
BCS
0
XLD
0
MUL4
0
3
1
1
0
0
VRS7
0
Figure 4-2. I/O Register Summary
2
1
1
0
0
VRS6
1
1
1
1
0
0
VRS5
1
Bit 0
1
1
0
0
VRS4
0
MC68HC08AZ32A Data Sheet, Rev. 2
62
Freescale Semiconductor