MC68HC08AZ32A Datasheet, PDF (252/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module A (TIMA)
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 1 and clear output on compare is selected, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 17-9 shows, the CHxMAX bit
takes effect in the cycle after it is set or cleared. The output stays at 100% duty cycle level until the
cycle after CHxMAX is cleared.
NOTE
The 100% PWM duty cycle is defined as a continuous high level if the PWM
polarity is 1 and a continuous low level if the PWM polarity is 0. Conversely,
a 0% PWM duty cycle is defined as a continuous low level if the PWM
polarity is 1 and a continuous high level if the PWM polarity is 0.
Table 17-2. Mode, Edge, and Level Selection
MSxB
X
X
0
0
0
0
0
0
0
1
1
1
MSxA
0
1
0
0
0
1
1
1
1
X
X
X
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Mode
Configuration
Output preset
Pin under port control;
initial output level high
Pin under port control;
initial output level low
Capture on rising edge only
Input capture
Capture on falling edge only
Capture on rising
or falling edge
Software compare only
Output compare ^{Toggle output on compare}
or PWM
Clear output on compare
Set output on compare
Buffered
output
compare or
buffered PWM
Toggle output on compare
Clear output on compare
Set output on compare
OVERFLOW
OVERFLOW
PERIOD
TCHx
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 17-9. CHxMAX Latency
MC68HC08AZ32A Data Sheet, Rev. 2
252
Freescale Semiconductor