MC68HC08AZ32A Datasheet, PDF (55/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
RESET
WRITE PTB/PTD
READ PTB/PTD
DDRBx/DDRDx
PTBx/PTDx
ADC DATA REGISTER
Functional Description
DISABLE
PTBx/PTDx
ADC CHANNEL x
DISABLE
CONVERSION
INTERRUPT ^COMPLETE
LOGIC
AIEN
COCO
CGMXCLK
BUS CLOCK
ADC VOLTAGE IN
ADC
ADCVIN
ADCH[4:0]
CHANNEL
SELECT
ADC CLOCK
CLOCK
GENERATOR
ADIV[2:0] ADICLK
Figure 3-2. ADC Block Diagram
3.3.2 Voltage Conversion
When the input voltage to the ADC equals V_REFH (see 20.7 ADC Characteristics), the ADC converts the
signal to $FF (full scale). If the input voltage equals AV_SS/V_REFL, the ADC converts it to $00. Input
voltages between V_REFH and AV_SS/V_REFL are a straight-line linear conversion. Conversion accuracy of
all other input voltages is not guaranteed. Avoid current injection on unused ADC inputs to prevent
potential conversion error.
NOTE
Input voltage should not exceed the analog supply voltages.
3.3.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status and control register, $0038), and requires
between 16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles
is a function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For
example, with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency
of 1 MHz, one conversion will take between 16 and 17 µs and there will be between 128 bus cycles
between each conversion. Sample rate is approximately 60 kHz.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
55