MC68HC08AZ32A Datasheet, PDF (200/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
15.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-4. This clock can
come from either an external oscillator or from the on-chip PLL. Chapter 4 Clock Generator Module
(CGM).
15.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four. Chapter 4 Clock Generator Module (CGM).
15.2.2 Clock Start-Up From POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has been completed. The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
15.2.3 Clocks in Stop and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. (See 15.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. However, some modules can be programmed to be active in
wait mode. Refer to the wait mode subsection of each module to see if the module is active or inactive in
wait mode.
OSC1
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
Figure 15-4. CGM Clock Signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
MC68HC08AZ32A Data Sheet, Rev. 2
200
Freescale Semiconductor