MC68HC08AZ32A Datasheet, PDF (31/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Section
2.2 I/O Section
Addresses $0000–$004F, shown in Figure 2-2, contain the I/O data, status and control registers
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
Name
Bit 7
Port A Data Register ^Read:
(PTA) Write:
See page 155. _Reset:
PTA7
Port B Data Register ^Read:
(PTB) Write:
See page 157. _Reset:
PTB7
Port C Data Register ^Read:
0
(PTC) Write:
See page 159. _Reset:
Port D Data Register ^Read:
(PTD) Write:
See page 161. _Reset:
PTD7
Data Direction Register A ^Read:
(DDRA) Write:
See page 155. _Reset:
DDRA7
0
Data Direction Register B ^Read:
(DDRB) Write:
See page 157. _Reset:
DDRB7
0
Data Direction Register C ^Read: _MCLKEN
(DDRC) Write:
See page 159. _Reset:
0
Data Direction Register D ^Read:
(DDRD) Write:
See page 162. _Reset:
DDRD7
0
Port E Data Register ^Read:
(PTE) Write:
See page 163. _Reset:
PTE7
Port F Data Register ^Read:
0
(PTF) Write:
See page 165. _Reset:
Port G Data Register ^Read:
0
(PTG) Write:
See page 167. _Reset:
Port H Data Register ^Read:
0
(PTH) Write:
See page 169. _Reset:
6
PTA6
5
PTA5
PTB6 PTB25
0
PTC5
PTD6
PTD5
DDRA6
0
DDRB6
0
0
0
DDRD6
0
PTE6
DDRA5
0
DDRB5
0
DDRC5
0
DDRD5
0
PTE5
PTF6
PTF5
0
0
0
0
= Unimplemented
4
3
2
1
PTA4
PTA3
PTA2
PTA1
Unaffected by reset
PTB4
PTB3
PTB2
PTB1
Unaffected by reset
PTC4
PTC3
PTC2 PTC1
Unaffected by reset
PTD4
PTD3
PTD2 PTD1
Unaffected by reset
DDRA4 DDRA3 DDRA2 DDRA1
0
0
0
0
DDRB4 DDRB3 DDRB2 DDRB1
0
0
0
0
DDRC4 DDRC3 DDRC2 DDRC1
0
0
0
0
DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
PTE4
PTE3
PTE2
PTE1
Unaffected by reset
PTF4
PTF3
PTF2 PTF1
Unaffected by reset
0
0
PTG2 PTG1
Unaffected by reset
0
0
0
PTH1
Unaffected by reset
R
= Reserved
Figure 2-2. I/O Data, Status and Control Registers (Sheet 1 of 6)
Bit 0
PTA0
PTB0
PTC0
PTD0
DDRA0
0
DDRB0
0
DDRC0
0
DDRD0
0
PTE0
PTF0
PTG0
PTH0
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
31