MC68HC08AZ32A Datasheet, PDF (225/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

SPTE SPTIE SPE
Queuing Transmission Data
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE SPRF
ERRIE
MODF
OVRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Figure 16-10. SPI Interrupt Request Generation
Two sources in the SPI status and control register can generate CPU interrupt requests:
• SPI receiver full bit (SPRF) — the SPRF bit becomes set every time a byte transfers from the shift
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
• SPI transmitter empty (SPTE) — the SPTE bit becomes set every time a byte transfers from the
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
16.7 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
to accept new data. Write to the SPI data register only when the SPTE bit is high. Figure 16-11 shows the
timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0).
For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having
to time the write of its data between the transmissions. Also, if no new data is written to the data buffer,
the last value contained in the shift register will be the next data word transmitted.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
225