MC68HC08AZ32A Datasheet, PDF (126/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

MSCAN08 Controller (MSCAN08)
11.9 Timer Link
The MSCAN08 will generate a timer signal whenever a valid frame has been received. Because the CAN
specification defines a frame to be valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal will be generated right after the EOF. A pulse of one bit time is generated.
As the MSCAN08 receiver engine also receives the frames being sent by itself, a timer signal also will be
generated after a successful transmission.
The previously described timer signal can be routed into the on-chip timer interface module B (TIMB). This
signal is connected to the channel 0 input under the control of the timer link enable (TLNKEN) bit in
CMCR0.
After the TIMB module has been programmed to capture rising edge events, it can be used under
software control to generate 16-bit time stamps which can be stored with the received message.
11.10 Clock System
Figure 11-8 shows the structure of the MSCAN08 clock generation circuitry and its interaction with the
clock generation module (CGM). With this flexible clocking scheme the MSCAN08 is able to handle CAN
bus rates ranging from 10 kbps up to 1 Mbps.
CGMXCLK
OSC
CGM
MSCAN08
÷2
PLL
CLKSRC
÷2
CGMOUT
(TO SIM)
BCS
÷2
(2 * BUS FREQUENCY.)
PRESCALER
(1 .. 64)
MSCANCLK
Figure 11-8. Clocking Scheme
MC68HC08AZ32A Data Sheet, Rev. 2
126
Freescale Semiconductor