MC68HC08AZ32A Datasheet, PDF (143/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Programmer’s Model of Control Registers
11.13.9 MSCAN08 Identifier Acceptance Control Register
Address: $0508
Bit 7
Read: 0
Write:
6
5
4
3
0
0
IDAM1 IDAM0
2
1
Bit 0
0
IDHIT1 IDHIT0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-24. Identifier Acceptance Control Register (CIDAC)
IDAM1–IDAM0— Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter organization (see 11.5 Identifier
Acceptance Filter). Table 11-9 summarizes the different settings. In “filter closed” mode no messages
will be accepted so that the foreground buffer will never be reloaded.
Table 11-9. Identifier Acceptance Mode Settings
IDAM1
0
0
1
1
IDAM0
0
1
0
1
Identifier Acceptance Mode
Single 32-bit acceptance filter
Two 16-bit acceptance filter
Four 8-bit acceptance filters
Filter closed
IDHIT1–IDHIT0— Identifier Acceptance Hit Indicator
The MSCAN08 sets these flags to indicate an identifier acceptance hit (see 11.5 Identifier Acceptance
Filter). Table 11-9 summarizes the different settings.
Table 11-10. Identifier Acceptance Hit Indication
IDHIT1
0
0
1
1
IDHIT0
0
1
0
1
Identifier Acceptance Hit
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
The IDHIT indicators are always related to the message in the foreground buffer. When a message gets
copied from the background to the foreground buffer, the indicators are updated as well.
NOTE
The CIDAC register can be written only if the SFTRES bit in the CMCR0 is
set.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
143