MC68HC08AZ32A Datasheet, PDF (205/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

15.4 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
Exception Control
15.4.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents onto the stack and sets the
interrupt mask (I-bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal processing can resume. Figure 15-9
shows interrupt entry timing, and Figure 15-10 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt may take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See Figure 15-10.
MODULE INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H
VECT L START ADDRESS
IDB
DUMMY ^{PC–1[7:0]} PC–1[15:8]
X
A
CCR V DATA H V DATA L OPCODE
R/W
Figure 15-9. Interrupt Entry
MODULE INTERRUPT
I-BIT
IAB
IDB
R/W
SP – 4 SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1[7:0] PC–1[15:8] OPCODE OPERAND
Figure 15-10. Interrupt Recovery
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
205