MC68HC08AZ32A Datasheet, PDF (202/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
IRST
RST
CGMXCLK
IAB
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 15-6. Internal Reset Timing
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 15-7. Sources of Internal Reset
Table 15-2. Reset Recovery Timing
Reset Recovery Type
POR/LVI
All Others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
15.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another 64 CGMXCLK cycles later, the CPU and memories are released from
reset to allow the reset vector sequence to occur.
At power-on, these events occur:
• A POR pulse is generated
• The internal reset signal is asserted
• The SIM enables CGMOUT
• Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow the
oscillator to stabilize
• The RST pin is driven low during the oscillator stabilization time
• The POR bit of the SIM reset status register (SRSR) is set
MC68HC08AZ32A Data Sheet, Rev. 2
202
Freescale Semiconductor