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MC68HC08AZ32A Datasheet, PDF (289/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit
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5.0 Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
Input high voltage (all ports, IRQ, RST, OSC1)
VIH
0.7 x VDD
VDD
V
Input low voltage (all ports, IRQ, RST, OSC1)
VIL
VSS
0.3 x VDD
V
VDD + VDDA supply current
Run(2) (3)
Wait(4) (3)
Stop(5)
25°C
–40°C to +125°C
25°C with LVI enabled
–40°C to +125°C with LVI enabled
—
30
mA
—
14
mA
IDD
—
50
µA
—
100
µA
—
400
µA
—
500
µA
I/O ports Hi-Z leakage current
IL
–1
1
µA
I/O ports Hi-Z leakage current(6)
IL
–10
10
µA
Input current
IIn
–1
1
µA
Input current
IIn
–10
10
µA
Capacitance
Ports (as input or output)
COut
CIn
—
—
12
8
pF
Low-voltage reset inhibit
Trip
Recover
VLVI
3.80
—
V
—
4.49
POR re-arm voltage(7)
VPOR
0
200
mV
POR reset voltage(8)
VPORRST
0
800
mV
POR rise time ramp rate(9)
RPOR
0.02
—
V/ms
High COP disable voltage(10)
VTST
VDD + 3
VDD + 4.5
V
Monitor mode entry voltage on IRQ(11)
VTST
VDD + 3
VDD + 4.5
V
1. VDD = 5.0 Vdc ± 0.5 V, VSS = 0 Vdc, TA = –40°C to TA (MAX), unless otherwise noted.
2. Run (Operating) IDD measured using external square wave clock source (fBUS = 8.4 MHz). All inputs 0.2 V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects run IDD. Measured with all modules enabled.
3. Although IDD is proportional to bus frequency, a current of several mA is present even at very low frequencies.
4. Wait IDD measured using external square wave clock source (fBus = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc loads.
Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD. Measured with all modules enabled.
5. Stop IDD measured with OSC1 = VSS.
6. When subjected to a Human Body Model (HBM) ESD event as specified in AEC Q100-002 these pins may exhibit
recoverable leakage values within the specification indicated.
7. Maximum is highest voltage that POR is guaranteed.
8. Maximum is highest voltage that POR is possible.
9. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
10. See Chapter 5 Computer Operating Properly (COP) Module. VTST applied to RST.
11. See monitor mode description within Chapter 5 Computer Operating Properly (COP) Module. VTST applied to IRQ or
RST.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
289
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