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MC68HC08AZ32A Datasheet, PDF (291/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit
5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing
20.8 5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing
Num(1)
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency(3)
Master
Slave
fBUS(M)
fBus(S)
fBUS/128
dc
fBUS/2
fBUS
MHz
Cycle time
1
Master
Slave
2
Enable lead time
3
Enable lag time
tCYC(M)
tCYC(S)
tLead
tLag
2
128
tCYC
1
—
15
—
ns
15
—
ns
Clock (SCK) high time
4
Master
Slave
tW(SCKH)M
100
—
ns
tW(SCKH)S
50
—
Clock (SCK) low time
5
Master
Slave
tW(SCKL)M
100
—
ns
tW(SCKL)S
50
—
Data setup time (inputs)
6
Master
Slave
tSU(M)
tSU(S)
45
—
ns
5
—
Data hold time (inputs)
7
Master
Slave
Access time, slave(4)
8
CPHA = 0
CPHA = 1
9
Slave disable time (hold time to high-impedance state)
Enable edge kead time to data valid(5)
10
Master
Slave
tH(M)
tH(S)
tA(CP0)
tA(CP1)
tDIS
tEV(M)
tEV(S)
0
—
ns
15
—
0
40
ns
0
20
—
25
ns
—
10
ns
—
40
Data hold time (outputs, after enable edge)
11
Master
Slave
12
Data valid
Master (before capture edge)
13
Data hold time (outputs)
Master (after capture edge)
tHO(M)
tHO(S)
tV(M)
tHO(M)
0
—
ns
5
—
90
—
ns
100
—
ns
1. Item numbers refer to dimensions in Figure 20-1 and Figure 20-2.
2. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins.
3. fBus = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state.
5. With 100 pF on all SPI pins
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
291