MC68HC08AZ32A Datasheet, PDF (258/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module B (TIMB)
Addr.
$0045
$0046
$0047
$0048
$0049
$004A
Name
Timer B Channel 0 Status ^Read:
and Control Register Write:
(TBSC0) See page 268. _Reset:
Timer B Channel 0 Register ^Read:
High (TBCH0H) Write:
See page 271. _Reset:
Timer B Channel 0 Register ^Read:
Low (TBCH0L) Write:
See page 271. _Reset:
Timer B Channel 1 Status ^Read:
and Control Register Write:
(TBSC1) See page 268. _Reset:
Timer B Channel 1 Register ^Read:
High (TBCH1H) Write:
See page 271. _Reset:
Timer B Channel 1 Register ^Read:
Low (TBCH1L) Write:
See page 271. _Reset:
Bit 7
CH0F
0
0
Bit 15
Bit 7
CH1F
0
0
Bit 15
Bit 7
6
CH0IE
0
14
5
MS0B
0
13
6
5
0
CH1IE
R
0
0
14
13
6
5
= Unimplemented
4
3
2
1
MS0A ELS0B ELS0A TOV0
0
0
0
0
12
11
10
9
Indeterminate after reset
4
3
2
1
Indeterminate after reset
MS1A ELS1B ELS1A TOV1
0
0
0
0
12
11
10
9
Indeterminate after reset
4
3
2
1
Indeterminate after reset
R
= Reserved
Figure 18-3. TIMB I/O Register Summary (Continued)
Bit 0
CH0MAX
0
Bit 8
Bit 0
CH1MAX
0
Bit 8
Bit 0
18.3.1 TIMB Counter Prescaler
The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin,
PTD4/ATD12/TBCLK. The prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMB status and control register select the TIMB clock source.
18.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0 through TBSC1
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel
registers, TBCHxH–TBCHxL. Input captures can generate TIMB CPU interrupt requests. Software can
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The free-running counter contents are transferred to the TIMB channel register (TBCHxH–TBCHxL, see
18.8.5 TIMB Channel Registers) on each proper signal transition regardless of whether the TIMB channel
flag (CH0F–CH1F in TBSC0–TBSC1 registers) is set or clear. When the status flag is set, a CPU interrupt
is generated if enabled. The value of the count latched or “captured” is the time of the event. Because this
value is stored in the input capture register 2 bus cycles after the actual event occurs, user software can
MC68HC08AZ32A Data Sheet, Rev. 2
258
Freescale Semiconductor