MC68HC08AZ32A Datasheet, PDF (40/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Memory
Table 2-1. Vector Addresses⁽¹⁾ (Continued)
Address
$FFF0
Vector
TIMA CH2 Vector (High)
High
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
TIMA CH2 Vector (Low)
TIMA CH1 Vector (High)
TIMA CH1 Vector (Low)
TIMA CH0 Vector (High)
TIMA CH0 Vector (Low)
PIT Vector (High)
PIT Vector (Low)
PLL Vector (High)
PLL Vector (Low)
IRQ Vector (High)
IRQ Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
Reset Vector (Low)
1. All available ROM locations not defined by the user will by default be filled
with the software interrupt (SWI, opcode 83) instruction — see Chapter 6
Central Processor Unit (CPU). Take this into account when defining vector
addresses. It is recommended that ALL vector addresses are defined.
2.5 Random-Access Memory (RAM)
Addresses $0050 through $044F are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64K byte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero there are 176 bytes of RAM. Because the location of the stack RAM is programmable,
all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is
moved from its reset location at $00FF, direct addressing mode instructions can efficiently access all page
zero RAM locations. Page zero RAM, therefore, provides an ideal location for frequently accessed global
variables.
Before processing an interrupt, the CPU uses 5 bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
MC68HC08AZ32A Data Sheet, Rev. 2
40
Freescale Semiconductor