MC68HC08AZ32A Datasheet, PDF (226/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Peripheral Interface (SPI)
WRITE TO SPDR ¹
SPTE
3
2
8
5
10
SPSCK (CPHA:CPOL = 1:0)
MOSI
SPRF
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
654321
654321
654
BYTE 1
BYTE 2
BYTE 3
4
9
READ SPSCR
6
11
READ SPDR
7
12
PU WRITES BYTE 1 TO SPDR, CLEARING
PTE BIT.
YTE 1 TRANSFERS FROM TRANSMIT DATA
EGISTER TO SHIFT REGISTER,
ETTING SPTE BIT.
PU WRITES BYTE 2 TO SPDR, QUEUEING
YTE 2 AND CLEARING SPTE BIT.
RST INCOMING BYTE TRANSFERS FROM SHIFT
HIFT REGISTER TO RECEIVE DATA REGISTER,
ETTING SPRF BIT.
5 BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING
SPTE BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT
DATA REGISTER TO SHIFT REGISTER,
SETTING SPTE BIT.
6 CPU READS SPSCR WITH SPRF BIT SET.
11 CPU READS SPSCR WITH SPRF BIT SET.
7 CPU READS SPDR, CLEARING SPRF BIT.
12 CPU READS SPDR, CLEARING SPRF BIT.
8 CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
9 SECOND INCOMING BYTE TRANSFERS FROM
SHIFT REGISTER TO RECEIVE DATA REGISTER,
SETTING SPRF BIT.
Figure 16-11. SPRF/SPTE CPU Interrupt Timing
16.8 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is
low. Whenever SPE is low, the following occurs:
• The SPTE flag is set
• Any transmission currently in progress is aborted
• The shift register is cleared
• The SPI state counter is cleared, making it ready for a new complete transmission
• All the SPI port logic is defaulted back to being general purpose I/O.
The following items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to set all control bits again when SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be
disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
MC68HC08AZ32A Data Sheet, Rev. 2
226
Freescale Semiconductor