MC68HC08AZ32A Datasheet, PDF (79/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

COP Control Register (COPCTL)
5.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
5.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
5.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
5.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the mask option register (MORA).
See Chapter 10 Mask Options.
5.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit, COPRS in the MORA register (see
Figure 10-1. Mask Option Register A (MORA)).
5.4 COP Control Register (COPCTL)
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
Read:
5
4
3
2
Low byte of reset vector
1
Bit 0
Write:
Reset:
Clear COP counter
Unaffected by reset
Figure 5-2. COP Control Register (COPCTL)
5.5 Interrupts
The COP does not generate CPU interrupt requests.
5.6 Monitor Mode
The COP is disabled in monitor mode when V_TST (see 20.5 5.0 Volt DC Electrical Characteristics) is
present on the IRQ pin or on the RST pin.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
79