MC68HC08AZ32A Datasheet, PDF (59/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Registers
Table 3-1. Mux Channel Select (Continued)
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Input Select
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
Range 01111 ($0F) to 11010 ($1A)
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
PTD3/ATD11
PTD4/ATD12/TBCLK
PTD5/ATD13
PTD6/ATD14/TACLK
Unused⁽¹⁾
Unused⁽¹⁾
Reserved
Unused⁽¹⁾
V_REFH(2)
AV_SS/V_REFL(2)
[ADC power off]
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
2. The voltage levels supplied from internal reference nodes as specified in the
table are used to verify the operation of the ADC converter both in production
test and for user applications.
3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Indeterminate after Reset
= Unimplemented
Figure 3-4. ADC Data Register (ADR)
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
ADIV2 ADIV1 ADIV0 ADICLK
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-5. ADC Input Clock Register (ADICLK)
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
59