MC68HC08AZ32A Datasheet, PDF (162/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Input/Output (I/O) Ports
13.5.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a 1 to a
DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
Address: $0007
Bit 7
Read:
DDRD7
Write:
Reset: 0
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Bit 0
DDRD0
0
Figure 13-12. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 13-13 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 13-13. Port D I/O Circuit
When bit DDRDx is 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0, reading
address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit. Table 13-4 summarizes the operation of the port D pins.
Table 13-4. Port D Pin Functions
DDRD
Bit
0
1
PTD
Bit
X⁽¹⁾
X
I/O Pin
Mode
Input, Hi-Z⁽²⁾
Output
Accesses to DDRD
Read/Write
DDRD[7:0]
DDRD[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Accesses to PTD
Read
Write
Pin
PTD[7:0]⁽³⁾
PTD[7:0]
PTD[7:0]
MC68HC08AZ32A Data Sheet, Rev. 2
162
Freescale Semiconductor