MC68HC08AZ32A Datasheet, PDF (204/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
15.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
NOTE
Extra care should be exercised if code in this part has been taken from
another M68HC08 with a different memory map since some legal
addresses could become illegal addresses on a smaller ROM. It is the
user’s responsibility to check their code for illegal addresses. Older
M68HC08s may have a different illegal address reset specification.
15.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V_DD voltage falls to the
LVI_TRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK cycles later,
the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down
the RST pin for all internal reset sources.
15.3.3 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly (COP) module. The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of
CGMXCLK.
15.3.4 SIM Counter During Power-On Reset
The power-on reset (POR) module detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
15.3.5 SIM Counter During Stop Mode Recovery
The SIM counter is also used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option
register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal applications should use the full
stop recovery time, that is, with SSREC cleared.
15.3.6 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 15.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states, see 15.3.2 Active Resets From Internal Sources for counter control and
internal reset recovery sequences.
MC68HC08AZ32A Data Sheet, Rev. 2
204
Freescale Semiconductor