MC68HC08AZ32A Datasheet, PDF (69/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

4.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the CPU interrupt signal generated by the PLL lock detector.
CGM Registers
4.5 CGM Registers
Three registers control and monitor operation of the CGM:
• PLL control register (PCTL)
• PLL bandwidth control register (PBWC)
• PLL programming register (PPG)
4.5.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock
selector bit.
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLLIE
PLLON
BCS
Write:
Reset: 0
0
1
0
1
1
1
1
= Unimplemented
Figure 4-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate a CPU interrupt request when the LOCK bit toggles,
setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as 0. Reset clears the PLLIE bit.
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates a CPU interrupt request if the
PLLIE bit also is set. PLLF always reads as 0 when the AUTO bit in the PLL bandwidth control register
(PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE
Do not inadvertently clear the PLLF bit. Be aware that any read or
read-modify- write operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See 4.3.3 Base Clock Selector
Circuit. Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
69