MC68HC08AZ32A Datasheet, PDF (277/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Monitor Module (MON)
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 15 BIT 13 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19-5. Break Address Register (BRKH)
Address: $FE0D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19-6. Break Address Register (BRKL)
19.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
19.2.3.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break wait bit (BW) in the SIM break status
register indicates whether wait was exited by a break interrupt. If so, the user can modify the return
address on the stack by subtracting one from it. See Chapter 15 System Integration Module (SIM).
19.2.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
19.3 Monitor Module (MON)
This subsection describes the monitor module (MON) and the monitor mode entry methods. The monitor
allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with
a host computer.
Features include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor ROM and host computer
• Standard mark/space non-return-to-zero (NRZ) communication with host computer
• Up to 28.8K baud communication with host computer
• Execution of code in RAM or ROM
• EEPROM programming
• ROM security (read protection)⁽¹⁾
• EEPROM read protection⁽¹⁾
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the ROM/EEPROM data
difficult for unauthorized users
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
277