MC68HC08AZ32A Datasheet, PDF (66/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
5. Calculate the bus frequency, f_BUS, and compare f_BUS with f_BUSDES.
f_Bus
=
-f-^C----^G-----^M----^V----^C----^L---^K--
4
Example:
f_BUS=
3----2-----M-----H----z--
4
=
8 MHz
6. If the calculated f_BUS is not within the tolerance limits of your application, select another f_BUSDES
or another f_RCLK.
7. Using the value 4.9152 MHz for f_NOM, calculate the VCO linear range multiplier, L. The linear range
multiplier controls the frequency range of the PLL.
L
=
rou
⎛
nd⎜
⎝
f--_{C----G--f-N--M--O--V---M-C---L----K--⎠⎟⎞}
Example:
L=
------3----2-----M-----H----z-------
4.9152 MHz
=
7
8. Calculate the VCO center-of-range frequency, f_CGMVRS. The center-of-range frequency is the
midpoint between the minimum and maximum frequencies attainable by the PLL.
f_CGMVRS = L × f_NOM
Example: f_CGMVRS = 7 × 4.9152 MHz = 34.4 MHz
NOTE
For proper operation:
f_CGMVRS – f_CGMVCLK
≤
-^f--^N---^O-----^M---
2
.
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent
of N.
b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent
of L.
4.3.2.5 Special Programming Exceptions
The programming method described in 4.3.2.4 Programming the PLL, does not account for two possible
exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for N is interpreted the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See
4.3.3 Base Clock Selector Circuit.
4.3.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
MC68HC08AZ32A Data Sheet, Rev. 2
66
Freescale Semiconductor