MC68HC08AZ32A Datasheet, PDF (290/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Electrical Specifications
20.6 Control Timing
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Bus operating frequency (4.5–5.5 V — V_DD only)
Internal clock period (1/f_Bus)
RST pulse width low
IRQ interrupt pulse width low (edge triggered)
IRQ Interrupt Pulse Period
f_Bus
—
8.4
t_CYC
119
—
t_RL
1.5
—
t_ILHI
1.5
—
t_ILIL
Note 3
—
MHz
ns
t_CYC
t_CYC
t_CYC
16-bit timer
Input capture pulse width⁽²⁾
Input capture period
Input clock pulse width
MSCAN wakeup filter pulse width⁽⁴⁾
t_TH, t_TL
2
—
t_TLTL
Note⁽³⁾
—
t_TCH, t_TCL
(1/f_OP) + 5
—
t_WUP
2
5
t_CYC
t_CYC
ns
µs
1. V_DD = 5.0 Vdc ± 0.5 V, V_SS = 0 Vdc, T_A = –40°C to T_{A (MAX)}, unless otherwise noted.
2. Refer to Table 17-2. Mode, Edge, and Level Selection, Table 18-2. Mode, Edge, and Level Selection, and supporting notes.
3. The minimum period t_TLTL or t_ILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus t _CYC.
4. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested.
20.7 ADC Characteristics
Characteristic⁽¹⁾
Min
Max
Unit
Comments
Resolution
8
8
Bits
Absolute accuracy
(V_REFL = 0 V, V_DDA = V_REFH = 5 V ± 0.5 V)
Conversion range
Powerup time
–1
V_REFL
16
+1
V_REFH
17
LSB
V
µs
Includes quantization
V_REFL = V_SSA
Conversion time period
Input leakage⁽²⁾ (ports B and D)
–1
1
µA
Input leakage⁽³⁾ (ports B and D)
–10
10
µA
Conversion Time
16
17
ADC clock cycles Includes sampling time
Monotonicity
Inherent within total error
Zero input reading
Full-scale reading
Sample time⁽⁴⁾
00
01
Hex
FE
FF
Hex
5
—
ADC clock cycles
V_IN = V_REFL
V_IN = V_REFH
Input capacitance
—
8
pF
Not tested
ADC internal clock
500 k 1.048 M
Hz
Tested only at 1 MHz
Analog input voltage
V_REFL V_REFH
V
1. V_DD = 5.0 Vdc ± 0.5 V, V_SS = 0 Vdc, V_DDA/V_DDAREF = 5.0 Vdc ± 0.5 V, V_SSA = 0 Vdc, V_REFH = 5.0 Vdc ± 0.5 V
2. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
3. When subjected to a Human Body Model (HBM) ESD event as specified in AEC Q100-002 these pins may exhibit recov-
erable leakage values within the specification indicated.
4. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
MC68HC08AZ32A Data Sheet, Rev. 2
290
Freescale Semiconductor