MC68HC08AZ32A Datasheet, PDF (203/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Reset and System Initialization
OSC1
PORRST
CGMXCLK
4096
CYCLES
32
CYCLES
32
CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 15-8. POR Recovery
15.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module timeout, a value (any value) should be written to location $FFFF. Writing to
location $FFFF clears the COP counter and bits 12 through 4 of the SIM counter. The SIM counter output,
which occurs at least every 8176 CGMXCLK cycles, drives the COP counter. The COP should be
serviced as soon as possible out of reset to guarantee the maximum amount of time before the first
timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at V_DD + V_TST while the MCU is in
monitor mode. The COP module can be disabled only through combinational logic conditioned with the
high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result
of external noise. During a break state, V_DD + V_TST on the RST pin disables the COP module.
15.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
203