MC68HC08AZ32A Datasheet, PDF (168/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Input/Output (I/O) Ports
PTG[2:0] — Port G Data Bits
These read/write bits are software-programmable. Data direction of each port G pin is under the control
of the corresponding bit in data direction register G. Reset has no effect on PTG[2:0].
KBD[2:0] — Keyboard Wakeup Pins
The keyboard interrupt enable bits, KBIE[2:0], in the keyboard interrupt control register (KBICR),
enable the port G pins as external interrupt pins. See Chapter 8 Keyboard Interrupt (KBD) Module.
Enabling an external interrupt pin will override the corresponding DDRGx.
13.8.2 Data Direction Register G (DDRG)
Data direction register G determines whether each port G pin is an input or an output. Writing a 1 to a
DDRG bit enables the output buffer for the corresponding port G pin; a 0 disables the output buffer.
Address: $000E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
DDRG2 DDRG1 DDRG0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-21. Data Direction Register G (DDRG)
DDRG[2:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins
as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 13-22 shows the port G I/O logic.
READ DDRG ($000E)
WRITE DDRG ($000E)
RESET
WRITE PTG ($000A)
DDRGx
PTGx
PTGx
READ PTG ($000A)
Figure 13-22. Port G I/O Circuit
MC68HC08AZ32A Data Sheet, Rev. 2
168
Freescale Semiconductor