MC68HC08AZ32A Datasheet, PDF (239/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Functional Description
Addr.
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
Name
Timer A Channel 2 Register ^Read:
Low (TACH2L) Write:
See page 253. _Reset:
Timer A Channel 3 Status ^Read:
and Control Register Write:
(TASC3) See page 249. _Reset:
Timer A Channel 3 Register ^Read:
High (TACH3H) Write:
See page 253. _Reset:
Timer A Channel 3 Register ^Read:
Low (TACH3L) Write:
See page 253. _Reset:
Timer A Channel 4 Status ^Read:
and Control Register Write:
(TASC4) See page 249. _Reset:
Timer A Channel 4 Register ^Read:
High (TACH4H) Write:
See page 253. _Reset:
Timer A Channel 4 Register ^Read:
Low (TACH4L) Write:
See page 253. _Reset:
Timer A Channel 5 Status ^Read:
and Control Register Write:
(TASC5) See page 249. _Reset:
Timer A Channel 5 Register ^Read:
High (TACH5H) Write:
See page 253. _Reset:
Timer A Channel 5 Register ^Read:
Low (TACH5L) Write:
See page 253. _Reset:
Bit 7
Bit 7
CH3F
0
0
Bit 15
Bit 7
CH4F
0
0
Bit 15
Bit 7
CH5F
0
0
Bit 15
Bit 7
6
5
6
5
0
CH3IE
R
0
0
14
13
6
5
CH4IE
0
14
MS4B
0
13
6
5
0
CH5IE
R
0
0
14
13
6
5
= Unimplemented
4
3
2
1
4
3
2
1
Indeterminate after reset
MS3A ELS3B ELS3A TOV3
0
0
0
0
12
11
10
9
Indeterminate after reset
4
3
2
1
Indeterminate after reset
MS4A ELS4B ELS4A TOV4
0
0
0
0
12
11
10
9
Indeterminate after reset
4
3
2
1
Indeterminate after reset
MS5A ELS5B ELS5A TOV5
0
0
0
0
12
11
10
9
Indeterminate after reset
4
3
2
1
Indeterminate after reset
R
= Reserved
Figure 17-3. TIMA I/O Register Summary (Continued)
Bit 0
Bit 0
CH3MAX
0
Bit 8
Bit 0
CH4MAX
0
Bit 8
Bit 0
CH5MAX
0
Bit 8
Bit 0
17.3.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin,
PTD6/ATD14/TACLK. The prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source.
17.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
239